1. Field of the Invention
The invention is related to the field of flash memory devices. More particularly, the invention relates to controlling data errors in the devices through various forms of decoding, error correction, and “wear concentration”.
2. Statement of the Problem
Flash memory is non volatile computer memory that can be electrically erased and reprogrammed and does not require power to maintain stored information. Additionally, flash memory offers relatively fast read access times and generally better kinetic shock resistance than hard disks. Another feature of flash memory is its durability, being able to withstand intense pressure, extreme temperatures, and even immersion in water. Such features are clearly advantageous to portable devices, such as cell phones, portable digital assistants (PDAs), and media players, such as the Apple, Inc. iPod.
Flash memory devices typically contain user data areas and overhead data areas. Such overhead information typically includes erase block management data and/or sector status information. Erase block management of a flash memory device generally provides logical sector to physical sector mapping.
Flash memory devices experience a greater incidence of errors than other forms of media due to increased memory cell densities, manufacturing inconsistencies, lower operating voltages, and, more particularly, excessive use of the devices. For instance, flash memory devices experience write fatigue over time which leads to less data integrity.
In some instances, flash memory devices are abstracted by various software drivers, management routines, and hardware support circuitry to hide defective regions from host systems to counter the errors. This abstraction of the memory device or computer usable storage is generally accomplished through the marking of bad memory blocks and their subsequent replacement with spare memory blocks. Additionally, error correction codes (ECCs) may be used to detect and correct data errors in retrieved data. ECCs may include block codes that are associated with a block of stored data or a data sector and stream codes that are typically utilized with streams of transmitted data. Error correction of data is generally done by a microprocessor or specialized hardware configured as an external microprocessor, a memory controller or within the memory device itself. Error correction is relatively complex and fairly processor intensive.
ECCs, and block codes in particular, are commonly based on specialized polynomial equations. Examples of such ECCs include Hamming codes, Reed-Solomon codes, Bose-Chaudhuri-Hochquenghem (BCH) codes, and cyclic redundancy check (CRC) codes. When the data is read out of a memory, the data integrity is checked by regenerating the coefficients embedded with the read data. The read data is passed through an ECC generator/checker to regenerate the ECC for comparison to the coefficients of the stored ECC. If the generated and stored ECCs do not match, an error has been detected. Once an error in the read data is detected, the transfer of the data out of the memory device is halted and the ECC correction algorithm initiates to correct the data error. However, an overhead cost is associated with the ECC. These overhead costs come in the form of increased storage space required for storing the ECC codes to allow detection and correction of errors in the stored data. In other words, ECCs generally require the association of extra bits to data and thus take away from the space available for data storage in a memory device.
Generally, the number of bits of an ECC determines the number of errors that can be detected and/or corrected. For instance, 1-bit ECC algorithms enable a set of symbols to be represented such that if one bit of the representation is incorrect, or “flipped”, the symbols will be corrected. 2-bit ECC algorithms enable a set of symbols to be represented such that if two bits of the representation are flipped or otherwise incorrect, the two bits will be corrected. Often, the use of a 2-bit ECC algorithm is preferred to a 1-bit ECC algorithm due to the ability of a 2-bit ECC algorithm to detect and correct more bits. However, the implementation of a 2-bit ECC algorithm, while providing increased error correction capabilities of stored data, generally involves more calculations and overhead than the implementation of a 1-bit ECC algorithm. When more computational overhead is required, more power is consumed by the flash memory device. As a result, the overall performance of a memory system may be compromised.
To reduce the computational and power requirements associated with implementing a 2-bit ECC algorithm, some systems may use 1-bit ECC algorithms to encode and to decode data, even though such algorithms are less accurate. In many cases, when a block is fairly new and has not been subjected to a relatively high number of erase/write cycles, a 1-bit ECC algorithm may be sufficient to ensure the integrity of much of the data. However, as a block gets older and subjected to a relatively high number of the erase/write cycles, a 1-bit ECC algorithm may not be sufficient to ensure a desired level of data integrity.
A hybrid ECC implementation enables a 1-bit ECC encoding and decoding of data in blocks which have undergone a relatively low number of erase/write cycles. For blocks which have undergone a relatively high number of erase/write cycles, a 2-bit ECC encoding and decoding of data is used. By dynamically determining when data is to be encoded using a more accurate algorithm, storage capacity decreases over time as opposed to an initial decrease of storage capacity through the use of a long term ECC algorithm. Moreover, the power requirements of the flash memory device increase over time via the dynamic allocation of ECC rather than the immediate power consumption associated with a larger ECC.
To implement the hybrid ECC algorithm, the flash memory device uses a threshold count of a number of erase/write cycles as an indicator of when to use a less calculation-intensive/lower accuracy ECC algorithm or a more calculation-intensive/higher accuracy ECC algorithm to encode data. For instance, when a comparison of the number of erase/write cycles undergone by a block breaches a threshold number of 100,000 erase/write cycles, then a higher accuracy ECC algorithm is used. In any case, the dynamic allocation of ECC still requires that space be allocated from the flash memory device thus reducing the overall capacity of the device.
Another manner of extending the usable life of the flash memory device regards the implementation of “wear leveling”. Wear leveling attempts to arrange data so that erasures and re-writes are distributed evenly across the flash memory cells of the flash device. In this way, no single sector prematurely fails due to a high concentration of erase/write cycles. A problem, however, exists with wear leveling as it still results in a substantial decrease in storage capacity over the useful life of the device by quickly decreasing the storage capacity of individual cells.